Memory errors are not rare
A large field study of Google’s server fleet, published in 2009, found that about a third of machines saw at least one correctable memory error per year — and that error rates were orders of magnitude higher than laboratory estimates. On a server that runs 24/7 for years, “it will never happen to me” is the wrong bet.
What ECC does
ECC memory stores extra check bits alongside the data. The memory controller uses them to correct single-bit errors on the fly and to detect multi-bit errors, instead of silently handing corrupted data to your application — or writing it to disk, where your filesystem would faithfully checksum the corrupted version.
DDR5’s on-die ECC is not the same thing
Every DDR5 chip includes on-die ECC, which fixes errors inside the chip itself. It does not protect data on its way between the module and the CPU, and it does not report anything to the operating system. True ECC modules add extra chips and a wider bus, so the memory controller can correct and log errors end to end. When we say ECC, we mean the latter: ECC UDIMMs on Ryzen, registered ECC RDIMMs on EPYC and Xeon.
Check it on your server
$ ls /sys/devices/system/edac/mc/
mc0
$ grep . /sys/devices/system/edac/mc/mc*/ce_count
/sys/devices/system/edac/mc/mc0/ce_count:0A memory controller listed under EDAC means error reporting is active. A rising ce_count (corrected errors) on one module is an early warning: open a ticket and we replace the module before it becomes a problem.
Sources
- B. Schroeder, E. Pinheiro, W.-D. Weber, “DRAM Errors in the Wild: A Large-Scale Field Study”, ACM SIGMETRICS 2009